1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly to, a semiconductor device capable of preventing electrostatic breakdown of its capacitor portion in a manufacturing process thereof.
2. Description of the Related Art
Of various semiconductor devices, a DRAM is capable of inputting/outputting of any information stored therein. Especially, such a memory device of DRAM comprised of memory cells each consisting of one transfer transistor and one capacitor is simple in construction and best in improvement in integration density of the semiconductor device, thus being prevalent in use all over the world.
Besides, a system LSI is considered to be important among the recent semiconductor devices. Among these semiconductor devices, a variety of mixed devices have been developed and discussed such as a logic circuit-mixed memory device in which logic and memory circuits are implemented on the same semiconductor chip, an analog circuit-mixed logic device in which logic and analog circuits are implemented on the same chip, etc. In these mixed devices also, as described above, each memory cell consists of one transfer transistor and one capacitor.
As the above-mentioned capacitor of each memory cell, such a three-dimensional one has been developed and used to accommodate a further increase in integration density of the semiconductor device. The capacitor has thus been made three dimensional for the following reasons. That is, it is essential to reduce the area occupied by the capacitor as the semiconductor device has been made finer in patterning and higher in integration density. To preserve stability and reliability in operation of the memory section of the semiconductor device, however, the capacitor must have at least a certain value of capacitance. As such, it has been necessary to change the construction of the capacitor electrode from a planar one to a three-dimensional one in order to increase the surface area of a lower electrode (information storing electrode) within a reduced occupied area.
There are two types of the three-dimensional constructions of the memory cell capacitors: a stack construction and a trench construction. Although they have merits and demerits, the stack construction has a higher margin against an xcex1-particle from the outside and noise from circuitry and so is stable in operation with a relatively small value of capacitance. For this reason, capacitors of the stack construction are regarded to be effective even with a design rule of 0.10 xcexcm or so of the semiconductor device.
Recently, the stack-construction capacitor (hereinafter called stack type capacitor) is required to have a dielectric film (capacitor insulator film) having a very high permittivity in order to preserve a predetermined value of capacitance in a small area region. As the high-permittivity film, such insulator films have been discussed aggressively as tantalum penta-oxide (Ta2O5) film, a SrTiO3 (hereinafter called STO film), (Ba, Sr)TiO3 (hereinafter called BST film), Pb(Zr, Ti)O3 (hereinafter called PZT film), etc. Further, a new conductive material has been required to make a lower electrode of the stack type capacitor. It is necessary to appropriately combine the above-mentioned high-permittivity insulating material and the lower electrode to thereby preserve a high reliability of the capacitor.
The following will describe a construction of a memory cell having a stack type capacitor made of a conventional high-permittivity film and a process for manufacturing the same with reference to FIGS. 8 and 9. FIG. 8 is a plan view for showing an end of a memory cell. FIG. 9 is a cross-sectional view taken along line C-D of FIG. 8. It is here to be noted that in FIG. 8, to make a problem clear, the cell plate electrode of a memory cell is hatched. Moreover, to simplify the drawing, only necessary components are shown, omitting the others.
As shown in FIG. 8, an element activation region surrounded by a trench element isolation region is formed. In each element activation region 102 are formed two memory cells. To connect these memory cells, word lines 102, 102a, 102b, 102c, 102d, 102e, 102f, 102g, etc. are arranged. Further, in capacitors of the memory cells are formed capacitor contact holes 103, 103a, . . . , respectively, over which are formed capacitor trenches 104, 104a, respectively in an inter-later insulator film described later. To cover this memory cell region thoroughly, a cell plate electrode 116 is formed.
Next, the manufacture of the above-mentioned memory cells is outlined with reference to FIG. 9. As shown in FIG. 9A, for example, on a P type silicon substrate 105 are selectively formed trench isolation regions 106 and 106a to thereby form the above-mentioned element activation region 101. On the silicon substrate 105 and the trench element isolation regions 106 and 106a are in turn formed word lines 102 and 102a and word lines 102b, 102c, and 102d respectively through a gate insulator film which provides a transfer-gate transistor of the memory cell. Then, a diffusion layer is formed in these word lines and trench element isolation regions in self-alignment to thereby form a diffused layer 107 for the bit line and diffused layers 108 and 108a for the capacitor.
Next, a first inter-layer insulator film 109 is formed to flatten the surface thoroughly. In this first inter-layer insulator film 109, a bit-line contact hole 110 is formed extending to the above-mentioned bit-line diffused layer 107 and filled with a bit-line plug 111. Similarly, in the above-mentioned first inter-layer insulator film 109, capacitor contact holes 103 and 103a are formed extending to the capacitor diffused layers 108 and 108a respectively and filled with capacitor plugs 112 and 112a respectively. It is here to be noted that the bit-line plug 111 and the capacitor plugs 112 and 112a are formed of a tungsten (W) film with a titanium nitride (TiN) film used as a barrier layer.
Next, a second inter-layer insulator film 113 is formed to flatten the above-mentioned first inter-layer insulator film 109, thus forming capacitor trenches 104 and 104a in a predetermined region. On the side surface and the bottom surface are in turn formed capacitors lower electrodes 114 and 114a respectively. It is here to be noted that the lower electrodes 114 and 114a are formed of a TiN film.
Next, a capacitor insulator film 115 is formed throughout the surface to cover a cell-plate metal film in order to form cell plate electrode 116. It is here to be noted that the capacitor insulator film 115 is made of tantalum penta-oxide formed to a thickness of 10 nm or so, while the cell-plate metal film is made of TiN. A resist mask 117 is used as an etching mask to pattern the above-mentioned cell-plate metal film by dry etching into a cell-plate electrode 116. An etchant gas used in this dry etching step is obtained by plasma-exciting a mixed gas composed of chloride (Cl2) and hydrogen bromide (HBr). It is here to be noted that by this dry etching step, the capacitor insulator film 115 is etched off partially.
Next, as shown in FIG. 9B, a third inter-layer insulator film 118 is formed to flatten the surface and cover the cell plate electrode 116. It is here to be noted that the third inter-layer insulator film 118 is obtained by flattening by Chemical Mechanical Polishing (CMP) a silicon oxide film formed by bias ECR (Electron Cyclotron Resonance).
Next, as shown in FIG. 9C, the above-mentioned third inter-layer insulator film 118 and the second inter-layer insulator film 113 are dry-etched to form a through hole 119 extending to the bit-line plug 111. Moreover, by the above-mentioned dry etching step, a cell-plate opening 120 is formed in the above-mentioned third inter-layer insulator film 118 so that it may reach the surface of the cell plate electrode 116.
Thus, the above-mentioned through hole 119 and cell-plate opening 120 are filled with a through-hole plug 121 and a cell-plate plug 122 respectively. Then, a bit line 123 is formed so as to connected to the above-mentioned through-hole plug 121, while a cell-plate wiring line 124 is arranged so as to connect to the above-mentioned cell-plate plug 122.
The inventor discussed in detail an MIM (Metal/Insulator/Metal) construction capacitor using the above-mentioned high-permittivity material as its capacitor insulator film. As a result, it was found that in an MIM construction capacitor, the above-mentioned capacitor insulator film frequently undergoes dielectric breakdown (electrostatic breakdown) during the process of manufacturing a semiconductor device if this capacitor insulator film is made of such oxidized metal as tantalum penta-oxide, zirconium dioxide (ZrO2), hafnium dioxide (HfO2), STO, BST, PZT, etc. As such, the inventor checked in detail the semiconductor device manufacturing process.
This phenomenon of electrostatic breakdown of the capacitor insulator film is described with reference to FIGS. 9 as follows. At the step of dry-etching the cell-plate metal film described with reference to FIG. 9A, the cell-plate metal film is charged by a number of ions or electrons produced by plasma excitation of the etchant gas. Such charging at the time of dry-etching step may break down the capacitor insulator film 115 dielectrically in some cases.
Furthermore, at the step of forming the third inter-layer insulator film 118 described with reference to FIG. 9B, plasma-enhanced CVD (PECVD) by use of HDP (High Density Plasma) is employed. In this case also, the cell plate electrode 116 is charged by a number of ions or electrons. Such charging at the time of film forming step will break down the capacitor insulator film 115 dielectrically.
Further, at the step of dry etching described with reference to FIG. 9C for forming the through hole 119 and the cell plate opening 120, a fluoro-carbon-based halogen compound is plasma-excited is used as the etchant gas. In this case also, the cell plate electrode 116 is charged by the ions or electrons in the plasma. In this case, the through hole 119 must be formed by performing dry etching on the third inter-layer insulator film 118 and the second inter-layer insulator film 113. The cell plate opening 120, however, is formed by performing dry etching on the third inter-layer insulator film 118. As such, at the time of dry etching of the above-mentioned second inter-layer insulator film 113 after the above-mentioned third inter-layer insulator film 118 is etched, the cell plate electrode 116 is exposed to the above-mentioned plasma for long time. The capacitor insulator film 115 is, therefore, broken down dielectrically by charging at the time of this dry etching step.
It is an object of the present invention to provide a semiconductor device having an MIM construction capacitor that can prevent a capacitor insulator film of the capacitor from breaking down dielectrically due to charging at a step of manufacturing the semiconductor device.
A semiconductor device of the present invention comprises: a capacitor portion composed of a lower electrode, a capacitor insulator film, and an upper electrode; and a charging protection portion sharing the upper electrode and the capacitor insulator film. The lower electrode is electrically connected through the first contact plug provided in the inter-layer insulator film finally to the first diffused layer formed in the surface of the semiconductor substrate, the capacitor insulator film of the charging protection portion is adhered to the second contact plug provided in the inter-layer insulator film, which second contact plug is finally connected electrically to the second diffused layer formed in the surface of the semiconductor substrate, and the lower electrode is made of a first conductive material, while the first and second contact plugs are made of a second conductive material different from the first conductive material.